강연일자: 2020년 2월 12일(수)
강연시간: Short Course I (10:30~18:00), Short Course II (14:00~18:00)
IMEP-LAHC, Grenoble INP Minatec, France
Sorin Cristoloveanu received the PhD (1976) in Electronics and the French Doctorat? s-Sciences in Physics (1981) from Grenoble Polytechnic Institute, France. He is currently Director of Research CNRS. He also worked at JPL (Pasadena), Motorola (Phoenix), and the Universities of Maryland, Florida, Vanderbilt, Western Australia, and Kyungpook (World Class University project). He served as the director of the LPCS Laboratory and the Center for Advanced Projects in Microelectronics, initial seed of Minatec center. He authored more than 1,100 technical journal papers and communications at international conferences (including 160 invited contributions). He is the author or the editor of 28 books, and he has organized 25 international conferences. His expertise is in the area of the electrical characterization and modeling of semiconductor materials and devices, with special interest for silicon-on-insulator and ultrathin body structures. He has supervised more than 100 PhD completions. With his students, he has received 15 Best Paper Awards, an Academy of Science Award (1995), and the Electronics Division Award of the Electrochemical Society (2002). He is a Fellow of IEEE, a Fellow of the Electrochemical Society, and Editor of Solid-State Electronics. He is the recipient of the IEEE Andy Grove award 2017, the highest distinction of the Electron Device Society.
Cambridge Univ., UK분야: modern power devices
Cambridge Univ., UK
Florin Udrea is a professor in semiconductor engineering and head of the High Voltage Microelectronics and Sensors Laboratory at University of Cambridge. He received his BSc degree from Politehnica University of Bucharest in 1991, his Master degree in sensors from Warwick University, UK in 1992 and his PhD degree in power devices from the University of Cambridge, Cambridge, UK, in 1995. Since October 1998, Prof. Florin Udrea has been an academic with the Department of Engineering, University of Cambridge, UK. Between August 1998 and July 2003 he was an advanced EPSRC Research Fellow and prior to this, a College Fellow in Girton College, University of Cambridge. He is currently leading a research group in power semiconductor devices and solid-state sensors that has won an international reputation during the last 25 years. Prof. Udrea has published over 450 papers in journals and international conferences. He holds over 100 patents with 20 more patent applications in power semiconductor devices and sensors. Prof. Florin Udrea founded five companies, Cambridge Semiconductor (Camsemi) in power ICs - sold to Power Integrations, Cambridge CMOS Sensors (CCS) in the field of smart sensors - sold to ams, Cambridge Microelectronics in Power Devices, Cambridge GaN Device in high voltage GaN technology and Flusso in Flow and temperature sensors. Prof. Florin Udrea is a board director in Cambridge Enterprise. For his ‘outstanding personal contribution to British Engineering’ he has been awarded the Silver Medal from the Royal Academy of Engineering. In 2015 Prof. Florin Udrea was elected a Fellow of Royal Academy of Engineering. In 2018 Prof. Udrea has been awarded several major prizes, including the Mullard medal from the Royal Society.
The power devices field has seen tremendous changes in the last decade. The traditional power MOSFET has been largely replaced by a new class of power devices based on the Silicon Sueprjunction concept, while the Insulated Gate Bipolar Transistors (IGBTs) are now fabricated on 12 inch wafers and have access to the latest thin wafer/trench/fine dimension technologies. The quest for high efficiency semiconductor devices for power electronics has led to the development of other materials, such as Gallium Nitride, Silicon Carbide Gallium Oxide and Diamond and other type of devices such as High Electron Mobility Transistors ( HEMTs), or MESFETs. This talk will cover a range of wide of power devices from silicon to those based on wide bandgap semiconductor technologies for diverse power electronics applications. New Figures of Merit (FOMs) will be defined for the materials and technologies of power devices. The talk will end with an outline of the challenges for the power electronics future and a vision of different technologies for the next 10 years.
Catholic Univ., Leuven, Belgium분야: RF circuits on FDSOI
Catholic Univ., Leuven, Belgium
Jean-Pierre RASKIN (IEEE M'97, IEEE SM’06, IEEE F’14) was born in Aye, Belgium, in 1971. He received the Industrial Engineer degree from the Institut Supérieur Industriel d'Arlon, Belgium, in 1993, and the M.S. and Ph.D. degrees in Applied Sciences from the Université catholique de Louvain (UCLouvain), Louvain-la-Neuve, Belgium, in 1994 and 1997, respectively. In 1998, he joined the EECS Department of The University of Michigan, Ann Arbor, USA. In 2000, he joined the Microwave Laboratory of UCLouvain, Louvain-la-Neuve, Belgium, as Associate Professor, and he has been a Full Professor since 2007. From September 2009 to September 2010, he was visiting professor at Newcastle University, Newcastle Upon Tyne, UK.
His research interests are the modeling, wideband characterization and fabrication of advanced SOI MOSFETs as well as micro and nanofabrication of MEMS / NEMS sensors and actuators, including the extraction of intrinsic material properties at nanometer scale.
He is IEEE Fellow, EuMA Associate Member, Société de l'électricité, de l'électronique et des technologies de l'information et de la communication (SEE) Member, and Material Research Society (MRS) Member. He was the recipient of the Médaille BLONDEL 2015, famous French reward that honors each year a researcher for outstanding advances in science which have demonstrated a major impact in the electrical and electronics industry. He received the SOI Consortium Award 2016 and the European SEMI Award 2017 in recognition in his vision and pioneering work for RF SOI. In 2017, he received with the NGO Louvain Cooperation the prestigious European Global Education Innovation Award. He is author or co-author of more than 350 scientific journal articles.
Today partially depleted SOI MOSFET is the mainstream technology for RF SOI systems. Future generations of mobile communication and computing systems will require transistors with better high frequency and high speed performance at lower power consumption. Fully Depleted (FD) SOI technology is foreseen as one of the best candidates and has been intensively studied these last years. Most of the reported data concern its digital performance. In this paper, the analog/RF behavior, self-heating characteristics, non-linear behavior as well as the wideband electrical performance at cryogenic temperature of FD SOI devices are presented. The impact of the handle silicon substrate on the high frequency performance of major RF/mm-waves integrated circuits will be demonstrated.
Stanford Univ., USA분야: 2D materials/devices
Stanford Univ., USA
Eric Pop is Professor of Electrical Engineering (EE) and Materials Science & Engineering (by courtesy) at Stanford, where he leads the SystemX Heterogeneous Integration focus area. He was previously on the faculty of UIUC (2007-13) and worked at Intel (2005-07). His research interests are at the intersection of electronics, nanomaterials, and energy. He received his PhD in EE from Stanford (2005) and three degrees from MIT (MEng and BS in EE, BS in Physics). His honors include the Presidential Early Career Award (PECASE), Young Investigator Awards from the Navy, Air Force, NSF and DARPA, and several best paper and best poster awards with his students. In 2018, he was named one of the world's Highly Cited Researchers by Web of Science. In his spare time he tries to avoid snowboarding injuries and in a past life he was a DJ at KZSU 90.1 FM, from 2000-04. Additional information about the Pop Lab is available online at http://poplab.stanford.edu.
Future technologies will need to process data in real-time, in an energy-efficient manner, a challenge which exposes the inefficiencies of traditional computing platforms. This tutorial will first introduce the 3D monolithic integration of logic, memory, and thermal management, which can yield up to 1000-fold energy-delay-product (EDP) benefits , especially in future abundant-data applications. Then, we will explore the role that 2D materials including graphene, boron nitride (h-BN) and transition metal dichalcogenides (TMDs) can play in such 3D systems. We will discuss the growth  and 3D heterogeneous integration of 2D materials. We will discuss how we could achieve sub-10 nm transistors [3,4] with 2D materials, which are compatible with or exceeding the performance of silicon electronics. We will also discuss the anisotropic thermal properties of 2D materials, which could be leveraged to block  or conduct heat away from 3D system hotspots, or as the basis of thermal transistors  to moderate heat spikes. Along the way, we will also illuminate some common pitfalls in the analysis of 2D materials, including how to correctly interpret mobility, contact resistance, and thermal conductivity measurements. In the end, this tutorial will reveal the role that 2D materials could play in future 3D nanosystems, taking advantage of their unique properties.
LETI, France분야: the state-of-the-art in Q-bits
Louis Hutin received the PhD degree in electrical engineering from Grenoble INP in 2010. His research focus is device integration for CMOS and beyond CMOS digital logic. He joined the University of California, Berkeley in 2010, where he worked towards scaling nanoelectromechanical relays for ultra-low-power logic and non-volatile memory. He returned in 2013 to CEA-Leti, primarily investigating possible implementations of quantum logic based on Si CMOS technology. Louis Hutin received the Norman Hackerman Young Author Award of the Electrochemical Society in 2009 for his work on Schottky junctions. He authored and co-authored more than 120 international communications in peer-reviewed journals and conference proceedings, and holds 13 patents.
By leveraging the phenomena of quantum superposition and entanglement, some specifically designed quantum algorithms  can achieve polynomial to exponential speed up when compared to their best classical counterparts, thus holding great promise for a variety of applications such as secure data exchange, database search, machine learning, and simulation of quantum processes. Quantum computers are envisioned as hybrid devices  where quantum cores operate in conjunction with classical circuitry, part of which is dedicated to programming, control and post-processing functions.
Among several potential platforms for implementing the quantum core, electrically-addressable solid-state qubits are in principle well-positioned for scaling up to the millions of qubits necessary to run useful, fault-tolerant calculations. This is especially true for Si spin qubits, which are encoded in the spin degree of freedom of one or several elementary charges -, confined by MOS Gates with characteristic dimensions of only a few tens of nanometers. Their recently demonstrated compatibility with standard CMOS technology - is an advantage in terms of fabricating large high-density arrays of Quantum Dots with controlled variability, but also in the perspective of seamless co-integration with the control electronics required for addressing, manipulation and readout of the qubits .
The typical energy scales between the spin states impose simultaneously i/ low temperature operation (~1K) and thus minimal dissipation; ii/ resonant transitions driven by high frequency input signals (>GHz); iii/ minimizing cross-talk in a high density environment. Additional constraints are set by Quantum Error Correction (QEC) protocols, notably in terms of parallelized reflectometry-based sensing and data transfer management. This talk will review our latest progress in the field of few Si spin qubits experiments -, and by sketching the contours of more extensible architectures, provide a glimpse of the engineering challenges to be tackled for the purpose of designing a fault-tolerant universal quantum computer.
Hyunsang Hwang received the B.S.(1988) from Seoul National University and Ph.D. (1992) in Materials Science from University of Texas at Austin. He was senior engineer of LG Semicon (1992~1997) and professor at Gwangju Institute of Science and Technology (1997~2012). In 2012, he joined the faculty in Department of Materials science at Pohang University of Science and Technology (POSTECH). He was visiting professor of Tsinghua University, China (2017), Stanford University (2007) and Oak Ridge National Lab.(2002). His current research interests include neuromorphic device, ReRAM, CBRAM and low-power LOGIC devices. He has published over 380 journal papers, 60 international patents and 33 IEDM/VLSI technology papers. He is fellow of The Korean Academy of Science and Technology.
Various RRAM synapse devices such as filamentary switching RRAM (HfOx, TaOx) with MLC characteristics, interface switching RRAM (Pr0.7Ca0.3MnO3, TiOx) with analog memory characteristics, HfZrOx ferroelectric device and 3-terminal synapse devices using proton and oxygen migration were investigated. By optimizing forming and potentiation/depression conditions, we could improve conductance linearity and MLC characteristics of filamentary synapse device. By controlling the reactivity of metal electrode and oxygen concentration in oxide, we can modulate the retention characteristics of interface synapse device. By separating electrodes for potentiation/depression and read mode, 3-terminal synapse exhibits better synapse performance.
Integrate and fire neuron (I&F) devices were investigated using various threshold switching (TS) devices such as NbO2 based Insulator-to-Metal Transition (IMT) device, Ovonic Threshold Switching (OTS) device, and atomic-switching TS device. We found that the off-state resistance (Roff) and switching time of the TS devices determine leaky/non-leaky characteristics and activation function of neuron, respectively. We have estimated the pattern recognition accuracy of MNIST handwritten digits and CIFAR-10 dataset.
서울대학교, 화학공학, 학사 (1990)
서울대학교, 화학공학, 석사 (1992)
M.I.T. 화학공학, 박사 (2000)
Applied Materials (2000 - 2004)
성균관대학교, 교수 (2004 - 현재)
일본 AIST 방문 연구원 (2010, 2017)
플라즈마 공정, 플라즈마 식각, 원자층 식각, 플라즈마 모니터링, 양자점 소재, 양자점 발광소자
KAIST, 재료공학, 학사 (1991)
KAIST, 재료공학, 석사 (1993)
KAIST, 재료공학, 박사 (1996)
LG반도체, 현대전자 (현 SK Hynix) (1996 - 2001)
세종대학교, 교수 (2001 - 현재)
미국 Stanford 방문과학자 (1996 - 1997)
한국반도체연구조합 전문위원 (2007 - 2012)
프랑스 INP Grenoble 방문과학자 (2015)
Atomic layer deposition (ALD) reaction mechanism - precursor development, DFT simulation, in-situ monitoring, precursor delivery system
Interconnect system - process integration, thermomechanical simulation (FEM)
반도체 소자의 고집적화를 위해 stack capacitor DRAM, FinFET, 3D V-NAND 등의 3차원 소자 구조가 사용되고 있습니다. 따라서 박막의 step coverage가 우수한 atomic layer deposition (ALD) 공정의 사용이 지속적으로 증가하고 있고, ALD 장비 및 공정소재 시장도 크게 성장하고 있습니다. Short Course 2 "ALD와 ALE 공정 및 소재"의 첫째 시간인 "3차원 반도체 소자를 위한 ALD 공정 기술"에서는 ALD 공정의 원리를 중심으로 ALD 공정의 현황 및 전망, 그리고 ALD 공정 개발에 필요한 핵심 사항을 설명합니다. 우선 ALD 공정의 원리와 장점을 설명하고 현재 사용되거나 연구되고 있는 다양한 공정을 소개합니다. (1) 기판표면과 precursor의 반응과 (2) 기판에 흡착된 precursor와 co-reactant의 반응으로 이루어지는 ALD 공정에 대해 growth per cycle, saturation curve, temperature window 등의 개념을 설명합니다. 3차원 소자에서 가장 중요한 특성인 step coverage에 영향을 미치는 인자들을 살펴봄으로써 step coverage를 향상시키는 방안을 알아봅니다. 마지막으로 ALD 공정 개발에 사용되는 실시간 모니터링 기술 및 전산모사 기술을 소개합니다.
한국과학기술원 화학과 학사 (2001)
한국과학기술원 화학과 석사 (2003)
한국과학기술원 화학과 박사 (2007)
한국화학연구원, 선임연구원 (2010 - 2016)
한국화학연구원, 책임연구원 (2016 - 현재)
University of Illinois at Urbana-Champaign, Materials Eng. Ph.D. (1984.08 - 1989.05)
서울대학교 공과대학 금속공학과 이학석사 (1981.03 - 1983.02)
한양대학교 공과대학 금속공학과 학사 (1977.03 - 1981.02)
Tektronix 연구원 (1989.08 - 1991.05)
TDK (Silicon Systems Inc) 연구원 (1991.05 - 1992.03)
성균관대학교 조교수/부교수/교수 (1992.03 - 현재)
University of California at Berkeley, 방문교수 (1999.8 - 2001.02 / 2009.08 - 2011.05)
국가지정연구실 (NRL) (2001 - 2006)
성균관대학교 Fellow 교수 (2004.03 - 2006.02)
한국학술진흥재단 Project Manager (2006.03 - 2007.02)
교육과학부 Post BK21 성균관대학교 전자재료사업단 단장 (2006.03 - 2009.02)
지경부 차세대성장동력 디스플레이사업단 단장/디스플레이 전락기술사업단장/국가과학기술위원회 주역산업 전문위원 (2007 - 2009)
연구재단 ICT 융합 CRB (2015.08 - 2017.07)
한국재료학회 부회장, 한국진공학회 부회장, 한국표면공학회 부회장 (2011 - 2015)
한국재료학회 회장 (2016)
한국반도체디스플레이기술학회 부회장 (2016 - 현재)
한국진공학회 회장 (2019.1 - 현재)
KAIST 전기 및 전자공학과, 박사 (2009)
KAIST 전기 및 전자공학과, 학사 (2004)
이화여자대학교 전자전기공학과 (2018 - 현재)
서울과학기술대학교 전기정보공학과 (2016 - 2018)
충남대학교 전자공학과 (2010 - 2016)
삼성전자 책임연구원 (2009 - 2010)
KAIST, 전기및전자공학부, 박사 (2017)
KAIST, 전기및전자공학부, 석사 (2014)
KAIST, 전기및전자공학부, 학사 (2012)
UNIST, 전기전자컴퓨터공학부, 조교수 (2018 - 현재)
KAIST, 정보전자연구소, 박사후연구원 (2017 - 2018)
최근 머신 러닝으로 대표되는 인공 지능 기술은 대량의 관측된 데이터를 기반으로 컴퓨터가 인간과 비슷한 인지 작업들을 처리하는 방식을 혁신적으로 변화 시키고 있습니다. 클라우드, 서비스, 자동차, 제조업 등 광범위한 산업들이 이 기술을 이용하게 되면서 해당 연산을 빠르고 에너지 효율적으로 처리할 수 있는 새로운 하드웨어에 대한 요구 또한 증가하고 있습니다. 따라서 산업계와 학계에서 많은 인공지능용 하드웨어 가속기들을 발표 하고 있으나, 아직은 여러 가지 한계가 존재하는 상황입니다. 본 발표에서는 가장 많이 쓰이는 인공 지능 알고리즘과 응용 도메인을 살펴보고, 이를 지원하는 인공 지능용 하드웨어 가속기들의 기술 동향을 살펴 봅니다. 또한 최신 기술 동향을 근거로 앞으로 어떠한 방향으로 발전되게 될지 전망해 보도록 합니다.
DRAM 스케일링이 지속될수록 DRAM 셀은 retention이 악화되고 있으며, radiation에 의한 soft-error 및 hard-error 등으로 신뢰성이 저하되는 어려움을 겪고 있다. 본 강연은 이러한 문제점을 극복할 수 있는 방법으로 메모리의 오류를 일부 허용하더라도 시스템에 영향을 최소화하는 Approximate DRAM이라는 새로운 개념을 소개한다.
KAIST 학사 (2002)
KAIST 석사 (2004)
KAIST 박사 (2008)
LG전자 휴대폰 사업부 기술 전략팀 (2009 - 2011)
Texas Instrument OMAP System Architect (2011 - 2013)
Qualcomm Snapdragon System Architect (2013 - 2015)
LG전자 SIC 센터 System Architect (2016 - 2017)
LG전자 MC사업본부 선행개발실장 (2018)
LG전자 MC사업본부 카메라개발실장 (2019 -)
A.I. 를 활용하는 기능들이 Camera / Video Application에서 어떻게 활용되고 있는지,
AP 내부에서는 어떤 Flow를 통해 A.I. 기능이 구현되고 있는가
현재 기술 제약은 어떤 부분인가?
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