Didier Landru
Soitec

Dr. Didier LANDRU obtained his PhD in material science from the University of Grenoble, France in 2000. He started his carrier in the industry as a development engineer in the STMicroelectronics Crolles manufacturing facility. From 2000 to 2006, he worked on the industrialization of advanced CMOS processes into the R&D pilot line. In 2006, he joined the SOITEC Company as a scientist where he is in charge of developing innovative substrates and processes for microelectronic. His main areas of expertise are silicon-on-insulator wafers, layer transfer, wafer bonding and 3D integration. He is the author and co-author of more than 50 patents related to electronic substrates and processes.

Didier Landru
Soitec

The Physics of SOI Manufacturing

Emerging electronic applications such as Internet-Of-Things (IOT), mixed signal processing or silicon photonics require silicon-on-insulator substrates (SOI) with very challenging specifications. For example, as threshold voltage of FD-SOI transistor depends directly on the thickness of the top silicon layer, the thickness and the surface roughness have to be controlled within extremely tight tolerance. The SmartCut^TM process is the only technology compatible with high volume manufacturing that allows transferring extremely thin layers of crystalline material with respect to these requirements. Furthermore, the layer transfer can be achieved on a wide range of functionalized handling substrates that can bring an additional gain to the final device.
This tutorial aims to describe the key challenges in manufacturing this new generation of SOI substrates. First, a review of the modern applications of SOI will be done, highlighting the specificity in terms of specifications. Then, the SOI manufacturing challenges will be described, from the physical modeling of fabrication processes to the need of developing new dedicated metrologies. Finally, some examples will be detailed for the most successful devices on the market.

Stéphane Bernabé
LETI, Grenoble

Stéphane Bernabé received an M.Sc. degree in Physics and Photonics engineering from the University Louis Pasteur of Strasbourg, France, in 1997. The same year, he graduated from the Ecole Nationale Sup?rieure de Physique de Strasbourg (ENSPS). Following several positions as R&D Engineer, Opteoelectronic packaging specialist and module architect in SMEs and start-up (Wavetek, Radiall, Intexys Photonics), he joined CEA-LETI’s Photonics Division in Grenoble, France, in 2007. As project leader and packaging expert, he was involved in several research activities dealing with Photonic Device integration, LED and PIC module packaging, Circuit design, Assembly techniques and reliability. He is currently leading the Photonic Interconnect activity within the Silicon Photonics laboratory, leading several French and European funded projects with applications to Telecommunications, Datacom, and High Performance Computing using Optical Networks On Chip. He is author/co-author of more than 50 publications or conference proceedings , two book chapters and more than 15 patents in his field and currently serves as member of the Technical committee for several conferences (ECTC, ESTC, and IPC).

Stéphane Bernabé
LETI, Grenoble

Silicon Photonics: Interconnects and Co-Integrated Hybrid Devices

This tutorial reviews the state-of-the-art of photonic devices fabricated on silicon technology platform. The following aspects are addressed:
• Optical interconnects : why ?
• From microoptics to Photonic Integrated Circuits
• Silicon photonics : basics, devices, process flow
• From PIC to modules
• Main challenges (Electronic-photonic integration, laser diode integration, fiber coupling)
• Beyond datacenter modules (System In Package, Intra Chip communications)
• Roadmap and emerging applications

Sylvain Barraud
LETI, Grenoble

Sylvain Barraud received the Ph.D. degree from the Paris-Sud University, Orsay, France, in 2001. From 1998 to 2001, he worked at Institut d’Electronique Fondamentale (IEF), Orsay, France, on modeling and simulation of electron transport in field-effect transistors using Monte-Carlo method. He joined the French Atomic Energy Commission Laboratory (CEA-LETI), Grenoble, as a research staff member in 2001. From 2001 to 2009, he was engaged in the physics and modeling of transport in advanced MOSFET devices. Since 2010, his research activity is focused on innovative device integration. He has been involved in several industrial, european and national projects. His current research interests include the device physics, the fabrication and characterization of nanowire-based devices including tri-gate, omega-gate, and stacked-gate-all-around nanowire MOSFETs. In 2014 he received the IEEE Electron Devices Society’s Paul Rappaport Award. He has authored or co-authored about 200 papers published in international journals and conferences.

Sylvain Barraud
LETI, Grenoble

Gate-All-Around NanoSheets Structures: The Last Chance to Keep Moore’ Law Alive?

Semiconductor nanowires have been extensively studied during the past two decades for a wide range of applications (electronics, photonics, plasmonics, photovoltaics, etc.). Recently, significant advances and progress have been made in the field of Si nanowire field-effect-transistors (FETs) for future electronics applications. Indeed, Gate-All-Around (GAA) FETs have long been recognized as offering the best solution to short-channel-effects with a high current drivability per layout footprint due to 3D vertically stacked channels. Moreover, horizontal GAA NanoWires (NW) and NanoSheets (NS) also have the advantage of being fabricated with minimal deviation from FinFET devices in contrast to vertical NWs which require more disruptive technological changes. For these reasons, the GAA stacked-wire MOSFET architecture is today regarded as an attractive option to push CMOS scaling beyond 5nm nodes. Although the first 3D GAA stacked-wires transistors were demonstrated ten years ago, significant progress have been reported during these last few years with aggressive 44/48nm CPP (Contacted Poly Pitch) ground rules.
In this lecture, I will describe research focused on Si/SiGe nanowires for nanoelecronics applications. After a brief introduction on the fabrication of semiconductor nanowires, electronic transport properties expected for such one-dimensional nanostructures will be analyzed. Key technological challenges will be discussed and recent research results presented. Width-dependent carrier mobility in Si NW/NS and FinFET will be analyzed, and intrinsic performance and design considerations of GAA structures will be discussed and compared to FinFET devices with a focus on electrostatics, parasitic capacitances and different layout options. In concluding, I will mention how Si/SiGe nanowire FETs can be suitable candidates for studying new generations of quantum electronics devices and biosensors

Jong-Ho Lee
Seoul National University

Jong-Ho Lee received the Ph.D. degrees from Seoul National University, Seoul, in 1993 in electronic engineering. In 1994, he was with the School of Electrical Engineering, Wonkwang University, Iksan, Chonpuk, Korea. In 2002, he moved to Kyungpook National University, Daegu Korea, as a Professor of the School of Electrical Engineering and Computer Science. Since September 2009, he has been a Professor in the School of Electrical and Computer Engineering, Seoul National University (SNU), Seoul Korea. He has been director of Inter-University Semiconductor Research Center (ISRC) at SNU since January 2018. From August 1998 to July 1999, he was with Massachusetts Institute of Technology, Cambridge, as a postdoctoral fellow. He has authored or coauthored 258 papers published in refereed journals and about 400 conference papers related to his research and has been granted 99 patents in this area. Prof. Lee is IEEE Fellow and a Lifetime Member of the Institute of Electronics Engineers of Korea (IEEK). He has been served as a subcommittee member of IEDM, ITRS ERD member, a general chair of IPFA2011, and IEEE EDS Korea chapter chair. He received 30 awards for excellent research papers and research excellence.

Jong-Ho Lee
Seoul National University

Neuromorphic Devices and Concepts

Beginning with a brief introduction of artificial intelligence that has recently attracted attention, the technology includes software and hardware-based deep neural networks (DNNs) and spiking neural networks (SNNs). We will introduce some alternatives to imitate synapses when implementing artificial intelligence in semiconductor technology, and briefly discuss their advantages and disadvantages. Describe the results obtained by applying the STDP learning rule in a spiking neural network using some storage-based synaptic imitation devices as arrays. In addition to discussing the linearity of synaptic devices, an example of on-chip learning in a DNN is introduced. We introduce important weight update methods for DNN learning in hardware, and compare them in terms of accuracy. How to improve linearity in charge storage based synaptic imitation devices is discussed. Also discussed are the normalization and quantization needed to copy the learned weight on off-chip to the synapse array for inference. It is also briefly discussed how low power neurons that can generate spiking pulses are implemented. Finally, we discuss the development direction and application of artificial intelligence semiconductors.

Sorin Cristoloveanu
IMEP-LAHC, Grenoble INP Minatec

Sorin Cristoloveanu received the PhD (1976) in Electronics and the French Doctorat ?s-Sciences in Physics (1981) from Grenoble Polytechnic Institute, France. He is currently Director of Research CNRS. He also worked at JPL (Pasadena), Motorola (Phoenix), and the Universities of Maryland, Florida, Vanderbilt, Western Australia, and Kyungpook (World Class University project). He served as the director of the LPCS Laboratory and the Center for Advanced Projects in Microelectronics, initial seed of Minatec center. He authored more than 1,100 technical journal papers and communications at international conferences (including 160 invited contributions). He is the author or the editor of 28 books, and he has organized 25 international conferences. His expertise is in the area of the electrical characterization and modeling of semiconductor materials and devices, with special interest for silicon-on-insulator and ultrathin body structures. He has supervised more than 100 PhD completions. With his students, he has received 15 Best Paper Awards, an Academy of Science Award (1995), and the Electronics Division Award of the Electrochemical Society (2002). He is a Fellow of IEEE, a Fellow of the Electrochemical Society, and Editor of Solid-State Electronics. He is the recipient of the IEEE Andy Grove award 2017, the highest distinction of the Electron Device Society.

Sorin Cristoloveanu
IMEP-LAHC, Grenoble INP Minatec

A selection of possible nano-devices

There is urgent need for low-power and sharp-switching devices. Albeit many concepts have been promoted, most are not realistic enough to succeed on the marketplace. We will discuss in detail the device physics, architecture, and applications of selected promising devices. Several ideas for improving the performance of tunneling FETs are proposed. It will be demonstrated that band-modulation devices have real potential for fast logic, memory, and sensing, while maintaining full compatibility with CMOS. Their sharp-switching capability will be compared with that of ferroelectric and NEMS devices. On the other hand, the gate-induced ‘electrostatic doping’ is a unique feature of nano-size structures. The original undoped body turns at demand into N-doped or P-doped region, according to the polarity of the gate bias. This doping metamorphosis offers unrivalled flexibility for conceiving novel and reconfigurable devices. Examples of implementation in FD-SOI technology, nanowires, and 2D materials will be given.?

이 가 원 교수
충남대학교

학력
한국과학기술원 전자공학과 학사 (1994)
한국과학기술원 전자공학과 석사 (1996)
한국과학기술원 전자공학과 박사 (1999)

경력
2005 ~ 현재 : 충남대학교 전자공학과, 교수
1999 ~ 2005 : ㈜ SK하이닉스반도체, 책임연구원

주요 연구 분야
Flash Memory Cell, TMO Device, Device Simulation

정 수 옥 연구위원
SK하이닉스

학력
KAIST, 재료공학, 박사 (2000)
KAIST, 전자재료공학 석사 (1995)
KAIST, 전자재료공학 학사 (1993)

경력
2018 ~ 현재 : SK 하이닉스, 연구위원 (차세대 DRAM 플랫폼 요소기술 발굴 및 개발)
2010 ~ 2017 : SK 하이닉스, 수석연구원 (차세대 DRAM 플랫폼 준비 및 선행 기술 개발 리더 / 신 메모리 국제공동연구 프로젝트)
2000 ~ 2009 : SK 하이닉스, 책임연구원 (T100~T40 DRAM 선행 기술 개발 PI / 신 메모리 소자 기술 센싱 및 개발)

강연개요
지난 30년간 DRAM은 Technology node를 지속적으로 감소시키면서, 고객이 요구하는 bit growth 증가율과 제품 성능 개선을 지속적으로 이루어 왔습니다. 10nm tech node에 접어들면서 더욱더 많은 기술적, 경제적 장애 요인이 등장하고 있으며, 보다 창조적이고 혁신적인 구조와 공정 기술의 발전과 함께, 새로운 물질의 개발도 중요해 지고 있습니다.
다음과 같은 목차로 진행될 예정입니다.
- DRAM 구조, 제조 방법, 동작 (Write/Retention/Read) 방법
- DRAM scaling에 따른 risk 및 극복 : Cell transistor / Cell capacitor / 공정
- 미래 DRAM 기술

변 대 석 마스터
삼성전자

학력
서울대학교 학사 (1992)
서울대학교 박사 (1999)
ISSCC Memory Committee (2007 ~ 2010)
Author of 40 papers and over-130 patents

연구 경력
2014 ~ 현재 : 삼성전자, Master (차세대 VNAND 기술 개발 / New Memory 설계 기술 개발)
2007 ~ 2013 : 삼성전자, 수석 (32nm/42nm, 3 & 2bit/cell NAND 양산 제품 개발 리더)
2000 ~ 2006 : 삼성전자, 책임 (63nm/90nm/120nm NAND 양산 제품 개발 리더 / DFT 개발 (Electrical Fuse, Pin Reduction etc))

하 만 륜 수석
DB하이텍

학력
경북대학교, 전자공학과 학사 (1997)
KAIST, 전기및전자공학과 석사 (2000)
KAIST, 전기및전자공학과 박사 (2004)

경력
2005 ~ 2008 : MagnaChip Semiconductor
2009 ~ Present : DB Hitek

민 경 원 수석
전자부품연구원

경력
1996 ~ 현재 : 전자부품연구원 모빌리티플랫폼 연구센터 팀장/수석

강연개요
자율주행 자동차 소개(현황 및 주요 센서)
자율주행 자동차용 인공지능
자율주행 자동차 구현을 위한 요구사항

연 규 봉 센터장
자동차부품연구원

이력
자동차부품연구원 스마트운전제어연구센터장 (공학박사)
자동차 ADAS 분야
자동차용 반도체 적용분야